DRF1203 1000v, 12a, 30mhz the DRF1203 hybrid includes a high power gate driver and the power mosfet. the driver output can be con gured as inverting and non- inverting. it was designed to provide the system designer increased exibility and lowered cost over a non-integrated solution. typical applications ? class c, d and e rf generators ? switch mode power ampli ers ? pulse generators ? ultrasound transducer drivers ? acoustic optical modulators features ? switching frequency: dc to 30mhz ? low pulse width distortion ? single power supply ? 1v cmos schmitt trigger input 1v hysteresis ? inverting non-inverting select ? rohs compliant ? switching speed 3-4ns ? b vds = 1kv ? i ds = 12a avg. ? r ds(on) .90 ohm ? p d = 560w symbol parameter ratings unit v dd supply voltage 15 v in, fn input single voltages -.7 to +5.5 i o pk output current peak 8a t jmax operating and storage temperature 175 c mosfet driver hybrid driver absolute maximum ratings driver speci cations symbol parameter min typ max unit v dd supply voltage 10 15 v in input voltage 3 5.5 in (r) input voltage rising edge 3 ns in (f) input voltage falling edge 3 i ddq quiescent current 2ma i o output current 8a c iss input capacitance 3 r in input parallel resistance 1m v t(on) input, low to high out (see truth table) 0.8 1.1 v v t(off) input, high to low out (see truth table) 1.9 2.2 t dly time delay (throughput) 38 ns t r rise time 5 ns t f fall time 5 t d prop. delay 35 microsemi website - http://www.microsemi.com 050-4974 rev c 9-2010
DRF1203 mosfet absolute maximum ratings symbol parameter min typ max unit bv dss drain source voltage 1000 v i d continuous drain current t hs = 25c 12 a r ds(on) drain-source on state resistance 0.90 t jmax operating temperature 175 c mosfet dynamic characteristics symbol parameter min typ max unit c iss input capacitance 2000 pf c oss output capacitance 165 c rss reverse transfer capacitance 75 mosfet thermal characteristics symbol parameter min type max unit r jc thermal resistance junction to case 0.53 c/w r jhs thermal resistance junction to heat sink 0.141 t jstg storage temperature -55 to 150 c p dhs maximum power dissipation @ t sink = 25c 1060 w p dc total power dissipation @ t c = 25c 2830 microsemi reserves the right to change, without notice, the speci cations and information contained herein. 050-4974 rev c 9-2010 figure 1, DRF1203 simpli ed circuit diagram the simpli ed DRF1203 circuit diagram is illustrated above. by including the driver high speed by-pass capacitor (c1), their contributio n to the internal parasitic loop inductance of the driver output is greatly reduced. this, coupled with the tight geometry of th e hybrid, allows optimal gate drive to the mosfet. this low parasitic approach, coupled with the schmitt trigger input (in), kelvin signal grou nd (sg) and the anti-ring function, provide improved stability and control in kilowatt to multi-kilowatt, high frequency applications. the in pin is the input for the control signal and is applied to a schmitt trigger. both the fn and in pins are referenced to the kelvin ground (sg.) the signal is then ap- plied to the intermediate drivers and level shifters; this section contains proprietary circuitry designed speci cally for the ring abatement. the power drivers provide high current to the gate of the mosfets. symbol parameter min typ max unit c out output capacitance 2500 pf r out output resistance .8 l out output inductance 3 nh f max operating frequency cl = 3000nf + 50 30 mhz f max operating frequency rl = 50 50 driver output characteristics symbol parameter min typ max unit r jc thermal resistance junction to case 1.5 c/w r jhs thermal resistance junction to heat sink 2.5 t jstg storage temperature -55 to 150 c p djhs maximum power dissipation @ t sink = 25c 60 w p djc total power dissipation @ t c = 25c 100 driver thermal characteristics
the function (fn, pin 3) is the invert or non-invert select pin, it is internally held high. DRF1203 050-4974 rev c 9-2010 the test circuit illustrated above was used to evaluate the DRF1203 (available as an evaluation board drf12xx / evalsw.) the i nput control signal is applied to the DRF1203 via in(4) and sg(5) pins using rg188. this provides excellent noise immunity and cont rol of the signal ground currents. the +v dd inputs (2,6) are by-passed (c1,c2, c4-c9), this is in addition to the internal by-passing mentioned previously. the capacitor s used for this function must be capable of supporting the rms currents and frequency of the gate load. r l set for i dm at v ds max this load is used to evaluate the output performance of the DRF1203. figure 2, DRF1203 test circuit truth table *referenced to sg fn (pin 3)* in (pin 4)* mosfet high high on high low off low high off low low on microsemi?s products are covered by one or more of u.s. patents 4,895,810 5,045,903 5,089,434 5,182,234 5,019,522 5,262,336 6,5 03,786 5,256,583 4,748,103 5,283,202 5,231,474 5,434,095 5,528,058 6,939,743, 7,352,045 5,283,201 5,801,417 5,648,283 7,196,634 6,664,594 7,157, 886 6,939,743 7,342,262 and foreign patents. us and foreign patents pending. all rights reserved.
figure 3, DRF1203 mechanical outline all dimensions are .005 DRF1203 050-4974 rev c 9-2010 pin assignments pin 1 ground pin 2 +vdd pin 3 fn pin 4 in pin 5 sg pin 6 +vdd pin 7 ground pin 8 source pin 9 drain pin 10 source
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